Integrated circuit (IC) chips typically include multiple levels of conductive features which are vertically spaced apart and separated by intermediate insulating layers. Interconnections are formed between the levels of conductive features in the chip to provide high wiring density and good thermal performance. The interconnections are formed using lines and vias, which are etched through the insulating layers separating the levels conductive features of the device. The lines and vias are then filled with a conductive material to form interconnect structures (i.e., wires). Typically, a conductive metal, such as copper is used to form the interconnect structures.
Interconnects are commonly formed through a photolithography process that includes the deposition of a patternable masking layer commonly known as photoresist. One preferred photolithographic method of making interconnect structures is the damascene process. A typical damascene process includes: a blanket deposition of a dielectric material; patterning of the dielectric material using photoresist to form openings; deposition of a conductive material onto the substrate in sufficient thickness to fill the openings; and removal of the excessive conductive material from the substrate surface using a chemical reactant-based process, mechanical methods, or a combined chemical mechanical polishing (CMP) techniques.